中心博士生熊妮娜的工作——High-efficiency dual-level heterogenous grating coupler on CMOS-compatible silicon-lithium niobate platform（CMOS工艺兼容的硅-铌酸锂高效率双层异质光栅耦合器）的相关成果近期被Applied Physics Letters期刊接收发表，该工作得到了国家重点研发计划（2022YFB2803302）、国家自然科学基金（T2225023）的部分资助。由于铌酸锂光栅耦合器件的加工会引入锂离子污染，使之无法与成熟的CMOS工艺兼容，并且铌酸锂的波导刻蚀较为困难，使其耦合效率较低。本文在硅-铌酸锂硅平台上设计和制备了多层刻蚀的 CMOS 兼容型高效光栅耦合器。双层光栅耦合器由 90 nm 厚的硅波导和 220 nm 厚的硅光栅组成，光栅采用线性啁啾结构，无需蚀刻铌酸锂。这种设计改变了光栅的衍射特性，不仅减少了背反射，还改善了方向性和光纤到芯片的模式匹配。与现有研究相比，这项工作仅通过 CMOS 兼容蚀刻就实现了高耦合效率，无需额外的底部反射器或高指数叠层。理论计算预测，TE 模式的光纤到芯片耦合效率为 -1.76 dB，芯片外衍射效率为 -1.1 dB。实验测量的峰值耦合效率为 -2.84 dB，背反射低至 -26 dB。该光栅耦合器为硅和铌酸锂的单片集成铺平了道路。
摘要: We present the design and experimental demonstration of multilayer etched CMOS-compatible grating couplers with high efficiency on a heterogeneous silicon-lithium niobate platform. The dual-level grating coupler comprises 90 nm-thick Si waveguides and 220 nm-thick Si grating with a linear chirped structure without etching LN. The design changes the grating diffraction properties, which not only reduce back reflection but also improve directionality and fiber-to-chip mode match. In comparison with existing studies, this work achieves high coupling efficiency solely through CMOS-compatible etching without additional bottom reflectors or high-index overlays. Theoretical calculations predict a fiber-to-chip coupling efficiency of -1.76 dB and an off-chip diffraction efficiency of -1.1 dB for the TE mode. The experimental measurement of the peak coupling efficiency is -2.84 dB with the back reflection as low as -26 dB. The grating coupler paves the way for monolithic integration of Si and LN.